<?xml version="1.0" encoding="UTF-8"?><Articles><Article><id>514</id><JournalTitle>PROCESS VARIATION INDUCED MISMATCH ANALYSIS IN SENSE AMPLIFIERS</JournalTitle><Abstract>A Sense Amplifier is a very critical peripheral circuit in the memories as its performance strongly affects both the
memory access time and the overall memory power dissipation. As the device dimensions scale below 100 nm, the process
variations are increasing and are impacting the circuit design significantly. In this research paper, the effects of process
variation induced transistor mismatch on the sense amplifier performance are studied. A comparative study of the effect of
mismatch on the delay for different sense amplifier configurations at 45 nm technology is presented.</Abstract><Email>avd.a.deshpande@gmail.com</Email><articletype>Research</articletype><volume>6</volume><issue>8</issue><year>2016</year><keyword>Process Variation,Mismatch Analysis,Sense Amplifiers,SRAM,Voltage Mode Sense Amplifier,CMOS</keyword><AUTHORS>Abhinav V. Deshpande</AUTHORS><afflication>Plot No. 87, Pandurang Gawande Nagar, Behind Khamla Telephone Exchange, Khamla, Nagpur-440022, Maharashtra, India</afflication></Article></Articles>